1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, specifically to a semiconductor device having a low-resistant metal wire that is formed by using an electroplating technique and a method of manufacturing the semiconductor device. The term semiconductor device refers to devices in general that utilize semiconductor characteristics to function, and it includes a large-scale integrated circuit fabricated on a semiconductor substrate, a semiconductor display device in which circuits are built from thin film transistors formed on a transparent insulating substrate, and the like.
2. Description of the Related Art
Related art of the present invention are a technique of forming a copper (Cu) wire by a Damascene method in a large-scale integrated circuit (hereinafter abbreviated as LSI) and a technique of forming a thin film transistor (hereinafter abbreviated as TFT) that has a GOLD (acronym for gate-overlapped LDD) structure. The two techniques will be described as prior art.
[Copper Wire Forming Technique Using Damascene Method]
As micronization and densification are advanced in LSIs fabricated on silicon wafers or other semiconductor substrates, RC signal delay of wires is becoming the major factor that determines the operation speed of the LSIs. The advancement has also raised the need for a wire material that is lower in electric resistance than an aluminum (Al) wire conventionally used. Also a demand has risen as the current density is increased for a wire material more reliable than a conventional aluminum (Al) wire in terms of the ability of standing against electromigration (EM) and stress migration (SM). It is against this background that IBM (International Business Machines Corporation) developed a copper (Cu) wire forming technique using a Damascene method, which was presented at IEDM in 1997. With this as a turning point, semiconductor makers begun in earnest to develop a copper wire forming technique using a Damascene method. Now those techniques have already been put into practice in some of logic LSIs that have a design rule of 0.25 μm or less.
A copper wire forming technique using a Damascene method is a technique in which a given wire groove is formed in a part of an interlayer insulating film where a wire is to be formed, copper as a low-resistant wire material is embedded in the wire groove to form a copper film, and portions of the copper film that are outside the wire groove are removed by chemical mechanical polishing (hereinafter abbreviated as CMP) to form the wire while leaving copper inside the wire groove. There are two types of Damascene methods, a single Damascene method and a dual Damascene method. In a single Damascene method, a wire portion and a connection hole portion are formed separately whereas grooves of a wire portion and connection hole portion are formed and then copper is embedded in both grooves simultaneously in a dual Damascene method. The dual Damascene method is advantageous in cutting the process short since copper wires of the wire portion and connection hole portion are formed at the same time. On the other hand, the dual Damascene method has difficulty in forming a copper film by embedding in a connection portion of high aspect ratio (aspect ratio: 3 to 5). However, this difficulty is close to being solved because lately a technique of forming a copper film by embedding using electroplating has been established for a connection hole of high aspect ratio.
In the copper wire forming techniques described above, a copper wire has to be separated completely from the interlayer insulating film that is a silicon oxide film from two reasons; one is readiness of copper as a wire material for diffusion in a silicon oxide film and the other is oxidization of copper upon contact with the silicon oxide film. Accordingly, a thin diffusion preventing film for copper is formed in the groove so as to surround copper that is a wire material. As a technique for forming the diffusion preventing film, directional sputtering such as long throw sputtering and ionization sputtering, or MO (abbreviation for metal organic) CVD that uses an organic metal source has been developed. A high-melting point metal, nitride of a high-melting point metal, and a compound obtained by doping nitride of a high-melting point metal with silicon or boron are being examined as the material of the diffusion preventing film. Examples thereof include Ta, TaN, TaSiN, TiN, TiSiN, W, WN, WSiN, and WBN. On the diffusion preventing film, a thin copper seed layer is formed by directional sputtering or MO-CVD. The copper seed layer receives copper plating by electroplating, which is advantageous when the aspect ratio is high. Copper is thus embedded to form a film.
The copper wire forming technique using a Damascene method as this is a technique important and indispensable to a process of forming a multi-layer wire for a ultramicro LSI having a design rule of 0.25 μm or less. The Damascene method is an epoch-making technique that can achieve global planarization of a substrate in a process of forming a copper multi-layer wire and, since the wire is formed on a leveled surface, the technique is advantageous in electromigration (EM) and stress migration (SM). ArF excimer laser reduced projection exposure apparatus with the wavelength of exposure light set to 193 nm is employed to form an ultramicro pattern. While the ArF excimer laser reduced projection exposure apparatus is capable of resolving an ultramicro pattern of 0.2 μm or less, the apparatus has a problem of shallow penetration. The Damascen method is also advantageous in solving the problem of shallow penetration since the method achieves global planarization of a substrate.
The entirety of copper wire forming technique using a Damascene method is described in detail in, for example, “The Latest Development on Copper Wire Technique”, edited by Shozo Ninomiyahara, Nobuyoshi Kuriya, Kazuyoshi Ueno, and Nobuhiro Misawa, published by Realize Co. (SIPEC Corporation). Many other documents have been published and, for example, an MO-CVD technique for copper is described in an article written by Nobuyoshi Kuriya in “Semiconductor World”, December 1997, on pages 176 to 180. A directional sputtering technique is described in an article written by Nobuhiro Misawa in “Semiconductor World”, December 1997, on pages 186 to 191. For an electroplating technique for copper, see an article written by V. M. Dubin and four others in “Semiconductor World”, December 1997, on pages 192 to 196. A copper diffusion preventing film is described in an article written by Nobuyoshi Kuriya in “Semiconductor World”, February 1998, on pages 91 to 96.
[GOLD Structure TFT Forming Technique]
Polycrystalline silicon TFTs having high field effect mobility are attracting attention in semiconductor display devices whose circuits are built from TFTs on glass substrates or other transparent insulating substrates, for example, active matrix liquid crystal display devices. Polycrystal silicon films used in polycrystalline silicon TFTs have higher electric field effect mobility of holes and electrons than conventional amorphous silicon films. Therefore polycrystalline silicon films have an advantage of being capable of integrating not only transistors for pixels but also driver circuits that are peripheral circuits. For that reason, many makers are developing active matrix liquid crystal display devices with their circuits built from polycrystalline silicon TFTs.
However, despite their high electric field effect mobility, polycrystalline silicon TFTs sometimes suffer lowering of electric field effect mobility when continuously driven, as well as reduction in ON current (current flowing when a TFT is ON), an increase in OFF current (current flowing when a TFT is OFF), and other degradation symptoms, resulting in reliability problems. These degradation symptoms are called hot carrier phenomenon, which is known to be caused by hot carriers generated in a high electric field in the vicinity of a drain.
The hot carrier phenomenon was first found in a MOS (abbreviation for metal oxide semiconductor) transistor fabricated on a semiconductor substrate, and has been proved to be due to a high electric field near a drain. Various kinds of basic examinations have been conducted about countermeasures against hot carriers and, in MOS transistors having a design rule of 1.5 μm or less, an LDD (abbreviation for lightly-doped drain) structure is employed. In an LDD structure, a low concentration impurity region (n− region or p− region) is formed in an end of a drain utilizing a gate side wall and the impurity concentration in the drain junction is graded to relieve electric field concentration in the vicinity of the drain.
The LDD structure is fairly improved in drain withstand voltage compared to a single drain structure. On the other hand, the LDD structure is large in resistance of low-concentration impurity region (n− region or p− region) and therefore has a drawback of reduced drain current. In addition, the high electric field region is positioned right below the side wall and electrolytic dissociation by collision reaches the maximum in the region to implant hot electrons in the side wall. Accordingly, the low-concentration impurity region (n− region or p− region) is depleted and the resistance is increased, indicating a degradation mode unique to LDD, which has become a problem. The above problems become noticeable as the channel length is shortened. As a structure to overcome these problems in MOS transistors of 0.5 μm or less, a GOLD (acronym for gate-overlapped LDD) structure has been invented and employed in which a low-concentration impurity region (n− region or p− region) is formed so as to overlap an end of a gate electrode.
Under these circumstances, employing the LDD structure and the GOLD structure in polycrystalline silicon TFTs fabricated on glass substrates or other transparent insulating substrates is being considered for the purpose of relieving a high electric field near a drain as in the case of MOS transistors. If the LDD structure is employed in a polycrystalline silicon TFT, a low-concentration impurity region (n− region or p− region) functioning as an electric field relieving region is formed in a part of a polycrystalline silicon film that is outside a gate electrode and furthermore high-concentration impurity regions (n+ regions or p+ regions) functioning as a source region and a drain region are formed in parts of the polycrystalline silicon film that are outside the LDD region. While the LDD structure has an advantage of small OFF current, it has a drawback of being less effective in repressing hot carriers by relieving an electric field near a drain. On the other hand, if the GOLD structure is employed, the low-concentration impurity region (n− region or p− region) of the LDD structure is formed so as to overlap an end of a gate electrode and so the effect of repressing hot carriers is larger than the LDD structure. However, the GOLD structure has a drawback of large OFF current.
One of references on n-channel polycrystalline silicon TFTs having a GOLD structure is an article written by Mutuko Hatano, Hajime Akimoto and Takeshi Sakai in “IEDM 97 TECHNICAL DIGEST”, 1997, on pages 523 to 526. The article discloses the structure and basic characteristics of a GOLD structure TFT. In the GOLD structure TFT examined in the article, a gate electrode and a side wall for an LDD are formed of polycrystalline silicon, a low-concentration impurity region (n− region) functioning as an electric field relieving region is formed in a part of an active layer (formed of polycrystalline silicon) that is right below the side wall for an LDD, and high-concentration impurity regions (n+ regions) functioning as a source region and a drain region are formed in parts of the active layer that are outside the LDD region. According to the basic characteristics given in the article, the TFT can obtain a large drain current as the drain electric field is relieved and the effect of repressing drain avalanche hot carriers is large compared to ordinary LDD structure TFTs.
A Damascene method used in a process of forming a multi-layer wire for an ultramicro LSI having a design rule of 0.25 μm or less is an epoch-making technique that can achieve global planarization of a substrate. Since the Damascene method can form a level wire, it is advantageous in terms of reliability problems such as electromigration (EM) and stress migration (SM). Furthermore, the Damascene method is a breakthrough technique capable of solving the problem of shallow penetration of ArF excimer laser reduced projection exposure apparatus that is employed to form an ultramicro pattern.
However, the Damascene method has a problem of unusual scratch defects such as erosion and dishing generated on a surface polished in a CMP process for polishing a thick copper film that has been formed by electroplating. This leads to problems in yield and reliability. Although the scratch defects such as erosion and dishing described above are reduced by improvement of the CMP process, it is far from solving the problem completely. Accordingly, the copper wire forming technique using a Damascene method is not welcome in other processes than a multi-layer wire forming process for an ultramicro LSI having a design rule of 0.25 μm or less in which planarization in a wire forming process is indispensable and the merit of employing the technique is large. A simple technique of forming a low-resistant wire, which can be employed in the other processes, is therefore needed. The other processes mean single layer wire forming processes for a design rule of 0.25 μm or more which need to lower the wire resistance. Given as examples thereof are a process of forming a single-layer low-resistant wire in an LSI, and a process of forming a gate electrode and a wire in a semiconductor display device with its circuits built from polycrystalline silicon TFTs.